Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a fuse part for a semiconductor device employing a dual fuse.
If there is a failure in any one amongst the innumerable cells of a semiconductor memory device, the semiconductor memory device does not function and may be regarded as a defective product. Discarding the semiconductor memory device as a whole is quite ineffective in terms of production yield because the defect may have only occurred in some cells inside the semiconductor memory device. Therefore, the industry seeks to improve the production yield by preparing redundancy cells inside the semiconductor memory device in order to replace defective cells. This process is referred to as a repair process, and through the repair process, the whole semiconductor memory device is resuscitated.
A semiconductor device includes a fuse part for performing the above-described repair process. Typically, a fuse part includes a fuse and a fuse box, which is formed in a protective layer covering the fuse and allows access to a portion of the fuse. The fuse may be formed as a single fuse, which is formed of a single pattern according to the characteristics required by the semiconductor device or the fuse may be formed as a dual fuse, which is formed of a plurality of patterns spaced apart from each other on the same line by a predetermined distance.
FIGS. 1A and 1B illustrate a conventional fuse part of a semiconductor device employing a dual fuse according to prior art.
FIG. 1A is a plan view of the fuse part of the semiconductor device, and FIG. 1B is a cross-sectional view of the fuse part shown in FIG. 1A along a line X-X′. FIG. 2 is a photograph showing a concern with the conventional technology.
Referring to FIGS. 1A and 1B, the conventional fuse part of the semiconductor device includes a substrate 11, a dual fuse 14, a conductive pattern 12, a plurality of plugs 13, an insulation layer 15, a protective layer 16, a first fuse box 17A, and a second fuse box 17B. The dual fuse 14 includes a first pattern 14A and a second pattern 14B positioned to be spaced apart on the same line by a predetermined distance. The conductive pattern 12 is formed below the dual fuse 14. The plurality of the plugs 13 electrically connect the dual fuse 14 with the conductive pattern 12. The insulation layer 15 fills the space between the conductive pattern 12 and the dual fuse 14 and between the plugs 13. The protective layer 16 covers the dual fuse 14. The first and second fuse boxes 17A and 17B are formed in the protective layer 16 to partially expose the first and second patterns 14A and 14B, respectively.
One concern with the conventional fuse part is that its fuse box 17 may crack. It seems that the bottom surface of the fuse box 17 may crack as a result of stress that is concentrated at the edges of a bottom surface of the fuse box 17 due to the sharp edges of the bottom surface of the fuse box 17. Further, when a crack forms at the edges of the bottom surface of the fuse box 17 it may electrically disconnect the plugs 13, which electrically connect the first and second patterns 14A and 14B to the conductive pattern 12 (see reference symbol ‘A’ of FIG. 1B and FIG. 2). Thus, a repair fuse defect may occur because the dual fuse 14 which is not cut (i.e., a non-repair fuse) is recognized as a disconnected dual fuse 14 (i.e., a repair fuse).
As the integration degree of a semiconductor device increases and the size of the fuse part decreases, concern about the existence of a crack grows. Further, a crack is even more likely to occur due to a filler layer 18 filling the fuse box 17 during a package process. This is because as the size of the fuse part decreases, stress is more concentrated at the edges of the bottom surface of the fuse box 17, and the filler layer 18 increases the stress applied to the bottom surface of the fuse box 17.